1. Field of the Art
The present disclosure relates to grouping patterns of an integrated circuit (IC) design, and in particular to those patterns of the IC design in which lithographic distortions may occur, which are called “hotspots”.
2. Related Art
In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. To actually fabricate this circuit in a semiconductor substrate, the circuit must be translated into a physical representation, or layout, which itself can then be transferred onto a template (i.e. mask), and then to the silicon surface. Again, computer aided design (CAD) tools assist layout designers in the task of translating the discrete circuit elements into polygons which will embody the devices themselves in the completed IC. These polygons make up the individual components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, and so on.
Once the layout of the circuit has been created, the next step to manufacturing the IC is to transfer the layout onto a semiconductor substrate. One way to do this is to use the process of optical lithography in which the layout is first transferred onto a physical template which is in turn used to optically project the layout onto a silicon wafer.
In transferring the layout to a physical template, a mask (e.g. a quartz plate coated with chrome) is generally created for each layer of the integrated circuit design. This is done by inputting the data representing the layout design for that layer into a device such as an electron beam machine, which writes the IC layout pattern into the mask material. In less complicated and dense integrated circuits, each mask comprises the geometric shapes (polygons) which represent the desired circuit pattern for its corresponding layer. In more complicated and dense circuits in which the size of the circuit features approach the optical limits of the lithography process, the masks may also comprise optical proximity correction features such as serifs, hammerheads, bias and assist bars which are designed to compensate for proximity effects. In other advanced circuit designs, phase shifting masks may be used to circumvent certain basic optical limitations of the process by enhancing the contrast of the optical lithography process.
These masks are then used to optically project the layout onto a silicon wafer coated with photoresist material. For each layer of the design, a light is shone on the mask corresponding to that layer via a visible light source or an ultra-violet light source. This light passes through the clear regions of the mask, whose image exposes the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically, through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern which defines the geometries, features, lines and shapes of that layer. This process is then repeated for each layer of the design.
Optical proximity correction (OPC) applies systematic changes to geometries of the layout to improve the printability of a wafer pattern. Specifically, as the size of integrated circuit features drops to 0.18μ and below, the features can become smaller than the wavelength of the light used to create such features, thereby creating lithographic distortions when printing the features onto the wafer. These lithographic distortions can represent significant impacts on device performance.
Rule-based OPC can include rules to implement certain changes to the layout, thereby compensating for some lithographic distortions. For example, to compensate for line-end shortening, rule-based OPC may add a hammerhead to a line end. To compensate for corner rounding, rule-based OPC can add (or subtract) serif shapes from outer (or inner) corners. These changes can form features on the wafer that are closer to the original intended layout. Unfortunately, the more complex lithographic effects cannot be efficiently described by simple geometric rules.
In another type of resolution enhancement technique, lithographic simulation can be used to detect areas where lithographic distortions may occur, which are called “hotspots” herein. In model-based OPC, a real pattern transfer can be simulated (i.e. predicted) with a set of mathematical formulas (i.e. models). In this simulation, the edges of a feature (i.e. a polygon) in a layout can be dissected into a plurality of segments, thereby allowing these segments to be individually moved to correct for proximity effects. The placement of the dissection points is determined by the feature shape, size, and/or position relative to other features. Unfortunately, model-based OPC has a high computational cost, which makes it impractical for hotspot detection at early design stages.
Some features in a layout may not be lithographically resolved using rule-based or model-based OPC. In such cases, the foundry may issue a design rule change that prohibits such features from being used in a layout.
Currently, during a process ramp-up, one or more test chips may be fabricated to identify “hotspots”, i.e. specific patterns that are difficult to lithographically resolve. These hotspots are typically manually identified and placed in a hotspot file for further analysis. Notably, typical a hotspot file includes thousands of hotspots. Manually lithographically resolving each of these hotspots is tedious and time-intensive, thereby adding considerable expense to the process ramp-up.
Clustering hotspots into groups for analysis would save considerable time. For example, a first cluster of hotspots having a similar pattern could be lithographically resolved using design-based OPC, a second cluster of hotspots having a similar pattern (but different from the first cluster) could be lithographically resolved using model-based OPC, and a third cluster of hotspots having a similar pattern (and different from the first and second clusters) cannot be lithographically resolved, thereby resulting in a design rule change prohibiting that pattern. Clustering hotspots would accelerate the lithographic resolution for each type of pattern, rather than each pattern, thereby significantly increasing the efficiency and minimizing cost of the process ramp-up.
Therefore, a need arises for a technique that accurately characterizes hotspots at a reasonable computational cost.